The invention relates to a clock pulse counter and more particularly to such a counter designed to operate at a very high frequency.
This counter can for example be constituted by an integrated circuit comprising prediffused or master cells.
Conventionally, in order to realize a clock pulse counter, a large number of bit counting cells are associated and are in turn grouped into blocks.
FIG. 1 very schematically shows such an assembly wherein each block comprises four counting outputs OA, OB, OC and OD. All the blocks comprises a clock input OK receiving the same pulses to be counted, OK, a reset input R receiving the same reset signal, R, and a transfer input T receiving a same transfer order, T. Each block transmits to the input I of the following block a carry signal through a terminal C when all its bits are set to "1". Each block comprises counting flip-flops and latches wherein the content of all the counting flip-flops is transferred at the time a transfer order T is applied to the inputs T. This order T is synchronized again with the clock signal OK in order to memorize a stable information of the state of the counting outputs OA, OB, OC, OD.
A drawback of this conventional architecture lies in the fact that, when it is desired to count the clock pulses recurring at a very fast rate, all the blocks, that are identical, have to be carried out at the best of the manufacturing technology. As a result, all the flip-flops are realized according to critical design rules and the consumption of the circuit is liable to be very important. Consequently, the manufacturing performance of such counters, constituted for example by arrays of prediffused gates, is low.